1. Technical Field
The present disclosure relates generally to an apparatus and method for recovering the functionality of a central processing unit (CPU) core, and more particularly to an apparatus and method for recovering a CPU core to a safe state when a failure occurs in the CPU core due to an external cause, such as voltage, current, temperature, or the like, during the operation of the CPU core.
2. Description of the Related Art
A CPU core reads instructions from a storage medium, such as memory or a disk, performs a specific operation on an operand, and stores the result of the operation. Accordingly, a CPU core may be considered to be hardware or an IP that executes an algorithm for a specific application.
Central processing units (CPUs) are currently being widely used in all fields involving system semiconductors. The use of CPU cores has been expanded to various applications, including: high-performance media data processing for the processing of a large amount of multimedia data, such as the compression and decompression of video data, the compression and decompression of audio data, the deformation of audio data and sound effects; minimum performance microcontroller platforms for, for example, a wired/wireless communication modem, a voice codec algorithm, the processing of network data, a touch screen, a household electronic appliance controller, and motor control; and devices that cannot be stably supplied with power or cannot be supplied with power from the outside, such as a wireless sensor network and an electronics (smart) dust.
A CPU core is basically composed of a core, a translation lookaside buffer (TLB), and caches. A task that will be performed by a CPU core is stipulated by the combination of a plurality of instructions. That is, instructions are stored in memory, these instructions are sequentially input to the CPU core, and then the CPU core performs a specific operation at each clock cycle. The TLB functions to translate a virtual address into a physical address in order to drive an operating system-based application. The caches function to temporarily store the instructions, stored in the external memory, inside a chip, thereby increasing the speed of the CPU core.
Recently, in automobile systems, driver assistance systems, such as an advanced driver assistance system (ADAS), having high-level intelligence and precision have been actively developed, and thus the importance of electric or electronic device systems has increased.
In particular, it is expected that in order to recognize an environment outside a vehicle on behalf of a driver, applications in which a core having performance higher than the existing 50 to 100 MHz performance, i.e., a 500 MHz or higher performance CPU core, is applied to an automobile system are to increase considerably.
These applications include motion detection in a smart black box, pedestrian recognition during the running of a vehicle, the recognition of a driver's driving pattern or drowsiness, lane detection and driving assistance, etc.
In order to analyze a recognized external environment, a recognized image, a recognized voice and/or the input of a sensor and to be involved in the driving of a vehicle, the function of analyzing a large amount of data in real time using a high-performance CPU core and extracting a result, such as the recognition of a pedestrian, is required. In particular, in the case of lane recognition-based driving assistance, a direct influence may be exerted on a steering apparatus based on the result of recognition during the running of a vehicle. Methods of exerting a direct influence on a vehicle steering apparatus include a method of applying vibration to a steering wheel and a method of limiting the rotating angle of a steering wheel, as methods for notifying a driver of the result of lane recognition.
The importance of the function of identifying the reliability of a CPU core, i.e., a case in which a CPU core does not normally operate, is critical, particularly in applications that can recognize data outside a vehicle and exert a direct influence on the steering apparatus of the vehicle. The reason for this is that in the case in which a high-performance recognition result can exert a direct influence on a steering apparatus, when a semiconductor erroneously operates due to a cause, such as voltage, current, temperature, or the like, a direct influence may be exerted on a driver's life. Even in this high-performance CPU core, the result of the operation of a CPU core may exert an influence on steering, and thus the guarantee of the reliability of the operation of the CPU core, i.e., the guarantee of the operation of the CPU core that is performed according to an intended function, may be considered to be important.
The support of the functional safety of a semiconductor circuit means that when a fault that was not intended during the design of a circuit occurs in the circuit due to a certain external cause, the occurrence of a failure can be detected and the recovery of functionality can be performed. ISO 26262 assigns Automotive Safety Integrity Level (ASIL) classes according to circuit characteristics that can manage failures occurring in automobile semiconductor circuits as a standard for the design of the functional safety of automobile electric and electronic device systems which is defined by ISO TC22/SC3/WG16.
The fault that is not intended during the operation of a circuit refers to a phenomenon in which an external cause, i.e., particles, such as cosmic rays, newtons or muons, are accumulated in a semiconductor circuit and generate a bit-flip at an unspecific time. The lifetime of a bit-flip is known to generally range from 100 ps to 5 ns, and thus a normal state is recovered after the passage of a predetermined time. However, if a fault occurs in a storage device, i.e., a register file or a memory device, this value is continuously maintained, and thus causes a failure in a circuit. This leads to a failure in an overall system depending on the characteristics of the circuit and the location of the occurrence of the failure in the circuit, and thus acts as a risk factor that may cause a deadly accident.
The preceding technology related to the present invention includes U.S. Patent Application No. 2005-0102565 entitled “Fault-tolerant Multi-core Microprocessing” and U.S. Patent Application No. 2005-0015659 entitled “Targeted Fault Tolerance by Special CPU Instructions.”